• RISC-V logo. Source: Wikipedia 2018.
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  • HiFive Unleashed dev board from SiFive carrying Freedom U540 SoC. Source: SiFive Crowd Supply 2018.
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  • A comparison of open ISAs. Source: Asanović and Patterson 2014, pg. 2.
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  • Comparing code sizes in different ISAs. Source: Kanter 2016, fig. 3.
    image

RISC-V Architecture

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Summary

image
RISC-V logo. Source: Wikipedia 2018.

When computers "compute", they're in fact executing instructions that are defined by what's known as Instruction Set Architecture (ISA). Each computer hardware will support a particular ISA. RISC-V is a free, open ISA that can be extended or customized for a variety of hardware or application requirements.

Apart from defining the instructions themselves, to be a success, any ISA requires broad industry support from chip manufacturers, hardware designers, tool vendors, compiler writers, software engineers, and more. While RISC-V is still new, progress has been made in building a healthy ecosystem and first RISC-V chips have been released.

It's been said that,

The real value of RISC-V is enabling the software and tools community to develop around a single common hardware specification.

Milestones

2010

Researchers at the University of California, Berkeley conceive RISC-V (pronounced "risk five") as an ISA for research and education at Berkeley. Previously, they used SPARC ISA and a modified MIPS ISA but want a unified ISA for future projects. This is the fifth generation, following in the steps of four earlier generations in the 1980s.

May
2011

Version 1.0 of the RISC-V base user-level ISA is published as volume 1. This version is not frozen. Volume 2 is for supervisor-level ISA. About this time, Raven-1 testchip is taped out using ST 28nm FDSOI process node.

May
2014

Version 2.0 of the user-level ISA is published. This is a final frozen version.

2015

In January, the 1st RISC-V Workshop is organized in Monterey, CA. To drive the future development and adoption of RISC-V, RISC-V Foundation is established. With more than 100 member organizations, this is an open collaborative community including both hardware and software innovators.

Dec
2016

SiFive releases Freedom E310 32-bit microcontroller at 320 MHz. This is the first commercial RISC-V chip. The CPU core is SiFive E31 and its ISA is RV32IMAC.

Oct
2017
image

SiFive releases U54-MC Coreplex, the first RISC-V-based chip that supports Linux, Unix, and FreeBSD. It has 5 CPU cores: 4xU54 + 1xE51. This enables RISC-V processors to compete against ARM cores. In February 2018, SiFive releases a development board named HiFive Unleashed for this chip.

Jan
2018

It's reported that commercial players including Western Digital and Nvdia plan to use RISC-V ISA for their next generation of products.

Jul
2018

India's Shakti RISC-V processor at 400 MHz boots up Linux. The processor is based on Intel's 22nm FinFET process node.

Discussion

  • What's the motivation for creating RISC-V?
    An overview of RISC-V. Source: Linus Tech Tips 2018.

    Many of the world's PCs and laptops are based Intel's x86 architecture. Many of the world's smartphones and embedded devices are based on ARM architecture. Both are proprietary and any use of these architectures involve licensing cost and may involve royalty fees. Moreover, companies may lack full competency to design their proprietary ISA. Another problem is long-time support. For example, when DEC died, there was no one to support their proprietary ISAs Alpha or VAX.

    One researcher claimed that security flaws such as Meltdown and Spectre are down to flaws in Intel's instruction sets. This is less likely when ISAs are open to inspection by a wide engineering community.

    RISC-V is an open ISA. It uses BSD Open Source License. This license does not restrict even commercial use of the ISA. Anyone implementing RISC-V are not required to release the source code of their RISC-V cores. The license only requires that authors of RISC-V must be acknowledged. An open ISA will permit software reuse, greater innovation and reduced cost.

  • Do we need RISC-V when there are other open ISAs?
    image
    A comparison of open ISAs. Source: Asanović and Patterson 2014, pg. 2.

    Creators of RISC-V considered and dismissed other open ISAs. OpenRISC has technical shortcomings and little industry adoption. OpenSPARC is suitable for servers but not for embedded devices and smartphones. OpenSPARC is also licensed under GPLv2, which may not attract support from commercial players.

    RISC-V benefits from the mistakes of the past. It has no burden to support legacy instructions. It adopts RISC for its simplicity. By leaving out delayed branches, RISC-V is kept simple and clean. Other open ISAs are not modular. RISC-V is modular so that the right balance of cost and efficiency can be attained for a particular application. In particular, it can be customized for constrained IoT devices, smartphones/tablets or servers.

    One claim states that LatticeMico32 is an open source RISC processor that's some are already using and questions the need for RISC-V. They also state that the ecosystem is more important than having a perfect ISA.

  • What are some possible benefits of using RISC-V?

    Beyond saving on licensing or royalty fees, RISC-V has many benefits:

    • Universal: As one of its goals, RISC-V should suit all sizes of processors, all types of implementations (FPGA/ASIC/SoC), various software stacks, and various programming languages.
    • Modular: The ISA has a base specification plus optional extensions. This means designers can leave out stuff they don't need for their application.
    • Extensible: Designers can add custom instructions for specialized functions such as machine learning or security. This is particularly important when Moore's Law is ending.
    • Freedom: Designers have the freedom to work on their own optimized implementations and retain the choice to make their IP open.
    • Frozen: By freezing the ISA specifications, we can be certain that today's software and tools will work on RISC-V systems many decades from now.
    • Adoption & Reuse: By being open, RISC-V will encourage wider adoption because of compatibility. This enables reuse.
  • Could you compare RISC-V with alternative architectures?
    image
    Comparing code sizes in different ISAs. Source: Kanter 2016, fig. 3.

    In terms of code sizes, one study found RISC-V compressed ISA (RV32C) is similar to Thumb-2, while RV64C has better code density than its alternatives.

    In terms of performance (speed and power), there's no reason to believe that RISC-V processors will fare worse than ARM or x86 processors. It will be dependent on implementation: microarchitectural design, circuit design and processing technology.

  • Could you name some processors based on RISC-V?

    Because RISC-V is open, anyone can design and develop their own processors without licensing fees. However, design and engineering costs can run into millions of dollars plus a delayed time to market. It therefore makes sense to use IP cores or processors developed by others.

    Some offer RISC-V IP cores that chip makers can license. Among them are Andes Technology, Codasip, Bluespec, Cortus, and SiFive. There are others who offer soft cores that can run in FPGAs: Microsemi, Rumble Development, and VectorBlox.

    SiFive has two families of licensable cores: E Series and U Series. They also offer these in silicon plus their development boards. Freedom E310 (FE310) is the first member of the Freedom Everywhere family.

    India's Shakti is a RISC-V chip developed at IIT Madras.

    lowRISC is a fully open-sourced, Linux-capable, RISC-V-based SoC currently being developed. Their Rocket core currently runs on an FPGA.

    RISC-V Foundation maintains a list of RISC-V cores and SoCs.

  • What tools are available for developers who wish to work on RISC-V?

    Basic tools include compiler, assembler, disassembler, profiler, debugger, and linker. Beyond these are IDEs, SDKs, simulators, and many more.

    Tools are being developed and maintained by the team at UC Berkeley plus the wider community outside. RISC-V supports GNU/GCC, GNU/GDB and LLVM. Instruction Set Simulators (ISS) are available from Antmicro and QEMU. Full IDEs are available from Imperas, Microsemi and SiFive. SiFive's Eclipse-based IDE is called Freedom Studio. Tools are available to design your own RISC-V subsystem for FPGAs.

    RISC-V Foundation maintains the state of the current RISC-V software ecosystem.

  • Which operating systems have been ported to run on RISC-V?

    Different flavours of Linux have been ported to RISC-V, including Yocto. In January 2018, kernel version 4.6 was being used. Researchers at the University of Cambridge have ported FreeBSD. As on August 2018, 80% of Debian software library has been compiled for RISC-V. Fedora/RISC-V project aims to bring the Fedora experience on RV64GC architecture.

    Among the RTOS, Zephyr is planning a port as of August 2018. A port of FreeRTOS is also available.

References

  1. Asanović, Krste. 2018. "A Look Back at the Evolution of RISC-V and a Peek at What’s Next from Krste Asanović." RISC-V Blog, March 20. Accessed 2018-08-25.
  2. Asanović, Krste and David A. Patterson. 2014. "Instruction Sets Should Be Free: The Case For RISC-V." Technical Report No. UCB/EECS-2014-146, EECS Department, University of California, Berkeley, August 06. Accessed 2018-08-25.
  3. Codasip. 2018. "RISC-V Processors." Codasip. Accessed 2018-08-25.
  4. Fedora Project Wiki. 2018. "Architectures/RISC-V." August 18. Accessed 2018-08-27.
  5. Hill, M. D., D. Christie, D. Patterson, J. J. Yi, D. Chiou and R. Sendag. 2016. "Proprietary versus Open Instruction Sets." IEEE Micro, vol. 36, no. 4, pp. 58-68, July-Aug. Accessed 2018-08-25.
  6. Kanter, David. 2016. "RISC-V Offers Simple, Modular ISA." Microprocessor Report, The Linley Group, March 28. Accessed 2018-08-25.
  7. Lee, Yunsup. 2018. "Designing the Next Billion Chips: How RISC-V is Revolutionizing Hardware." The Linux Foundation YouTube, March 12. Accessed 2018-08-25.
  8. Linus Tech Tips. 2018. "An Open Source CPU!?" YouTube, August 22. Accessed 2018-08-25.
  9. Marena, Ted. 2018. "11 Myths About the RISC-V ISA." Electronic Design, January 31. Accessed 2018-08-25.
  10. McGregor, Jim. 2018. "The Difference Between ARM, MIPS, x86, RISC-V And Others In Choosing A Processor Architecture." Forbes, April 05. Accessed 2018-08-25.
  11. Microsemi. 2018. "RISC-V CPUs." Microsemi. Accessed 2018-08-25.
  12. Mithran, Athul. 2018. "Linux Boots On “Shakti” — India’s First Ever RISC-V Based Silicon Processor." Fossbytes, July 30. Accessed 2018-08-25.
  13. Oracle. 2018. "OpenSPARC T2." Accessed 2018-08-25.
  14. Patterson, David and Andrew Waterman. 2017. "The RISC-V Reader: An Open Architecture Atlas." First edition, 1.0.0, August 04.
  15. RISC-V Foundation. 2014. "RISC-V User-Level ISA Version 2.0 is released!" Blog, May 06. Accessed 2018-08-25.
  16. RISC-V Foundation. 2018a. "RISC-V Foundation." Accessed 2018-08-25.
  17. RISC-V Foundation. 2018b. "Workshops." Accessed 2018-08-25.
  18. RISC-V Foundation. 2018c. "FAQ." Accessed 2018-08-25.
  19. RISC-V Foundation. 2018d. "AB Open Article: Zephyr Project RTOS Gets RISC-V Partners, Board Support." Blog, August 20. Accessed 2018-08-26.
  20. Ray, Tiernan. 2018. "Western Dig, Nvidia On Board with ‘RISC-V,’ So Pay Attention, Says Benchmark." Barron's, January 03. Accessed 2018-08-25.
  21. SiFive. 2017. "SiFive Launches First RISC-V Based CPU Core with Linux Support." October 04. Accessed 2018-08-25.
  22. SiFive. 2018. "RISC-V Core IP." Accessed 2018-08-25.
  23. SiFive Crowd Supply. 2018. "HiFive Unleashed." SiFive at Crowd Supply. Accessed 2018-08-25.
  24. Wasserman, Aaron. 2018. "Why we need RISC-V." Hackernoon, January 04. Accessed 2018-08-25.
  25. Waterman, Andrew. 2016. "Design of the RISC-V Instruction Set Architecture." Technical Report No. UCB/EECS-2016-1, EECS Department, University of California, Berkeley, January 03. Accessed 2018-08-25.
  26. Waterman, Andrew and Krste Asanović, eds. 2017. "The RISC-V Instruction Set Manual. Volume I: User-Level ISA." Document Version 2.2, May 7. Accessed 2018-08-25.
  27. Waterman, Andrew, Yunsup Lee, David Patterson, and Krste Asanović. 2011. "The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA." Technical Report UCB/EECS-2011-62, EECS Department, University of California, Berkeley, May 13. Accessed 2018-08-25.
  28. Wikipedia. 2018. "RISC-V." August 25. Accessed 2018-08-25.
  29. Wiltz, Chris. 2017. "Linux Now Has its First Open Source RISC-V Processor." Design News, October 06. Accessed 2018-08-25.
  30. Wiltz, Chris. 2018. "First Open-Source RISC-V SoC for Linux Released." Design News, February 15. Accessed 2018-08-25.
  31. Wong, William. 2016. "First Open-Source RISC-V Chip Arrives." Electronic Design, December 02. Accessed 2018-08-25.
  32. lowRISC. 2015. "Untethered lowRISC release." December 18. Accessed 2018-08-25.

Milestones

2010

Researchers at the University of California, Berkeley conceive RISC-V (pronounced "risk five") as an ISA for research and education at Berkeley. Previously, they used SPARC ISA and a modified MIPS ISA but want a unified ISA for future projects. This is the fifth generation, following in the steps of four earlier generations in the 1980s.

May
2011

Version 1.0 of the RISC-V base user-level ISA is published as volume 1. This version is not frozen. Volume 2 is for supervisor-level ISA. About this time, Raven-1 testchip is taped out using ST 28nm FDSOI process node.

May
2014

Version 2.0 of the user-level ISA is published. This is a final frozen version.

2015

In January, the 1st RISC-V Workshop is organized in Monterey, CA. To drive the future development and adoption of RISC-V, RISC-V Foundation is established. With more than 100 member organizations, this is an open collaborative community including both hardware and software innovators.

Dec
2016

SiFive releases Freedom E310 32-bit microcontroller at 320 MHz. This is the first commercial RISC-V chip. The CPU core is SiFive E31 and its ISA is RV32IMAC.

Oct
2017
image

SiFive releases U54-MC Coreplex, the first RISC-V-based chip that supports Linux, Unix, and FreeBSD. It has 5 CPU cores: 4xU54 + 1xE51. This enables RISC-V processors to compete against ARM cores. In February 2018, SiFive releases a development board named HiFive Unleashed for this chip.

Jan
2018

It's reported that commercial players including Western Digital and Nvdia plan to use RISC-V ISA for their next generation of products.

Jul
2018

India's Shakti RISC-V processor at 400 MHz boots up Linux. The processor is based on Intel's 22nm FinFET process node.

Tags

See Also

  • RISC-V Instruction Sets
  • Reduced Instruction Set Computer
  • ARM Architecture
  • Instruction Set Architecture
  • Chisel (Language)
  • OpenSPARC

Further Reading

  1. Marena, Ted. 2018. "11 Myths About the RISC-V ISA." Electronic Design, January 31. Accessed 2018-08-25.
  2. Waterman, Andrew and Krste Asanović, eds. 2017. "The RISC-V Instruction Set Manual. Volume I: User-Level ISA." Document Version 2.2, May 7. Accessed 2018-08-25.
  3. Kanter, David. 2016. "RISC-V Offers Simple, Modular ISA." Microprocessor Report, The Linley Group, March 28. Accessed 2018-08-25.
  4. McGregor, Jim. 2018. "The Difference Between ARM, MIPS, x86, RISC-V And Others In Choosing A Processor Architecture." Forbes, April 05. Accessed 2018-08-25.
  5. Hill, M. D., D. Christie, D. Patterson, J. J. Yi, D. Chiou and R. Sendag. 2016. "Proprietary versus Open Instruction Sets." IEEE Micro, vol. 36, no. 4, pp. 58-68, July-Aug. Accessed 2018-08-25.
  6. Patterson, David and Andrew Waterman. 2017. "The RISC-V Reader: An Open Architecture Atlas." First edition, 1.0.0, August 04.

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Last update: 2018-08-28 04:37:07 by arvindpdmn
Creation: 2018-08-25 05:33:13 by hemanthSK

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Devopedia. 2018. "RISC-V Architecture." Version 9, August 28. Accessed 2018-09-25. https://devopedia.org/risc-v-architecture
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