RISC-V Instruction Sets

The design of RISC-V instruction sets is modular. Rather than take the approach of a large and complex monolith, a modular design enables flexible implementations that suit specific applications.

RISC-V defines base user-level integer instruction sets. Additional capability to these are specified as optional extensions, thus giving implementations flexibility to pick and choose what they want for their applications. The specifications of the base ISA has been frozen since 2014. Some of the extensions are also frozen while many others are being defined.

Discussion

  • Could you give an overview of RISC-V instruction set?
    RV32I instruction formats showing immediate variants. Source: Waterman and Asanović 2017, fig. 2.3.
    RV32I instruction formats showing immediate variants. Source: Waterman and Asanović 2017, fig. 2.3.

    RISC-V comprises of a base user-level 32-bit integer instruction set. Called RV32I, it includes 47 instructions, which can be grouped into six types:

    • R-type: register-register
    • I-type: short immediates and loads
    • S-type: stores
    • B-type: conditional branches, a variation of S-type
    • U-type: long immediates
    • J-type: unconditional jumps, a variation of U-type

    RV32I has x0 register hardwired to constant 0, plus x1-x31 general purpose registers. All registers are 32 bits wide but in RV64I they become 64 bits wide. RV32I is a load-store architecture. This means that only load and store instructions access memory; arithmetic operations use only the registers. User space is 32-bit byte addressable and little endian.

    Correspondingly, RV64I is for 64-bit address space and RV128I is for 128-bit address space. The need for RV128I is debatable and its specification is evolving. We also have RV32E for embedded systems. RV32E has only 16 32-bit registers and makes the counters of RV32I optional.

  • What RISC-V extensions have been defined?
    Versions of ISA base and extensions. Source: Waterman and Asanović 2017, pg. i.
    Versions of ISA base and extensions. Source: Waterman and Asanović 2017, pg. i.

    RISC-V defines a number of extensions, all of which are optional. Some of them are frozen and these are noted below:

    • M: Integer multiplication and division.
    • A: Atomic.
    • F: Single-precision floating point compliant with IEEE 754-2008.
    • D: Double-precision floating point compliant with IEEE 754-2008.
    • Q: Quad-precision floating point compliant with IEEE 754-2008.
    • C: Compressed instructions (16-bit instructions) to yield about 25-30% reduced code size. "RVC" refers to compressed instruction set.

    Among the evolving or future extensions are L (decimal float), B (bit manipulation), J (dynamically translated languages), T (transactional memory), P (packed SIMD), V (vector operations), N (user-level interrupts), and H (hypervisor support).

    When multiple extensions are supported, that ISA variant can be described by concatenating the letters; such as, RV64IMAFD. To represent the standard general purpose ISA, "G" is defined as a short form for "IMAFD".

    RV32I uses one-eighth of the encoding space. This means there's plenty of room for custom extensions.

  • What are pseudo-instructions?

    To ease the job of an assembly language programmer or a compiler writer, some base instructions can be represented by what are called pseudo-instructions. For example, a no operation is addi x0, x0, 0 for which nop is the pseudo-instruction. Likewise, branch if zero is beq rs, x0, offset for which beqz rs, offset is the pseudo-instruction.

  • What are privileged instructions?

    Application code usually runs in user mode or U-mode. RV32I and RV32G are user mode ISAs. Two more modes are available:

    • Machine mode (M-mode): For running trusted code. This is the most privileged mode in RISC-V and has complete access to memory, I/O and anything else to boot and configure the system. It's most important feature is to handle synchronous exceptions and interrupts. The simplest RISC-V microcontrollers need to support only M-mode.
    • Supervisor mode (S-mode): For supporting operating system needs of say Linux, FreeBSD or Windows. This is more privileged than U-mode but less privileged than M-mode. Where OS needs to process exceptions/interrupts, exception delegation is used to pass control to S-mode selectively. S-mode also provides a virtual memory system.
  • Could you describe some technical considerations in the design of RISC-V instructions?
    Comparing RISC-V RV32IMAF with Epiphany ISA. Source: Olofsson 2014, fig. 1.
    Comparing RISC-V RV32IMAF with Epiphany ISA. Source: Olofsson 2014, fig. 1.

    Design of RISC-V ISA considered cost, simplicity, performance, implementation-independence, room for growth, program size, and ease of use.

    RV32I includes generously 32 integer registers, making it easier for compilers to use them more often than memory. By keeping instructions simple, RISC-V instructions typically require only one clock cycle and deliver predictable performance. For dynamic linking, it adopts PC-relative branches.

    Instructions offer three register operands, avoiding the extra move required by ISAs with only two register operands. These are also in the same positions so that access can begin before decoding the instruction.

    The design was also informed by mistakes of other ISAs. For example, initial Alpha ISA did not have byte or half-word load/store. The shift operation in ARM can be seen as an overdesign. Delayed branches of MIPS and SPARC affected their ISAs. ARM Thumb and MIP16 added 16-bit instructions in hindsight.

  • Are RISC-V instructions without precedents?
    Desirable features as supported in earlier ISAs. Source: Waterman 2016, table 2.1.
    Desirable features as supported in earlier ISAs. Source: Waterman 2016, table 2.1.

    When we consider the 122 instructions of RV32G, only 6 of them are without precedents. 98 instructions appear in at least three prior ISAs. 18 instructions appear in one or two prior ISAs. This study included 18 prior RISC ISAs, including the CDC 6600 dating back to 1964.

    It's been commented that one cannot design a flawless ISA, nor an ISA with flaws doomed to fail.

Milestones

1981

RISC-I is defined by David A. Patterson at UC Berkeley as an alternative to increasingly complex instructions of the computers of the day. This is followed by RISC-II (1983), SOAR (1985) and SPUR (1986) projects.

2010

Researchers at the UC Berkeley conceive RISC-V as the fifth generation of their RISC design from the 1980s.

May
2011

Version 1.0 of the RISC-V base user-level ISA is published as volume 1. This version is not frozen. Volume 2 is for supervisor-level ISA.

May
2014

Version 2.0 of the user-level ISA is published. This is a frozen version.

May
2017

Version 2.2 of the user-level ISA is published. This does not modify the ISA base plus extensions IMAFDQ version 2.0. Extension C is frozen in this version.

References

  1. Asanović, Krste and David A. Patterson. 2014. "Instruction Sets Should Be Free: The Case For RISC-V." Technical Report No. UCB/EECS-2014-146, EECS Department, University of California, Berkeley, August 06. Accessed 2018-08-25.
  2. Chen, Tony and David A. Patterson. 2016. "RISC-V Geneology." EECS Department, University of California, Berkeley, January 24. Accessed 2018-08-25.
  3. Olofsson, Andreas. 2014. "Analyzing the RISC-V Instruction Set Architecture." Blog, Adapteva, August 11. Accessed 2018-08-25.
  4. Patterson, David A. and Carlo H. Sequin. 1981. "RISC I: A Reduced Instruction Set VLSI Computer." ISCA '81 Proceedings of the 8th Annual Symposium on Computer Architecture, pp. 443-457, May 12-14. Accessed 2018-08-25.
  5. Patterson, David and Andrew Waterman. 2017. "The RISC-V Reader: An Open Architecture Atlas." First edition, 1.0.0, August 04.
  6. RISC-V Foundation. 2014. "RISC-V User-Level ISA Version 2.0 is released!" Blog, May 06. Accessed 2018-08-25.
  7. Waterman, Andrew. 2016. "Design of the RISC-V Instruction Set Architecture." Technical Report No. UCB/EECS-2016-1, EECS Department, University of California, Berkeley, January 03. Accessed 2018-08-25.
  8. Waterman, Andrew and Krste Asanović, eds. 2017. "The RISC-V Instruction Set Manual. Volume I: User-Level ISA." Document Version 2.2, May 7. Accessed 2018-08-25.
  9. Waterman, Andrew, Yunsup Lee, David Patterson, and Krste Asanović. 2011. "The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA." Technical Report UCB/EECS-2011-62, EECS Department, University of California, Berkeley, May 13. Accessed 2018-08-25.

Further Reading

  1. Waterman, Andrew and Krste Asanović, eds. 2017. "The RISC-V Instruction Set Manual. Volume I: User-Level ISA." Document Version 2.2, May 7. Accessed 2018-08-25.
  2. Waterman, Andrew. 2016. "Design of the RISC-V Instruction Set Architecture." Technical Report No. UCB/EECS-2016-1, EECS Department, University of California, Berkeley, January 03. Accessed 2018-08-25.
  3. Chen, Tony and David A. Patterson. 2016. "RISC-V Geneology." EECS Department, University of California, Berkeley, January 24. Accessed 2018-08-25.
  4. Kanter, David. 2016. "RISC-V Offers Simple, Modular ISA." Microprocessor Report, The Linley Group, March 28. Accessed 2018-08-25.

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Cite As

Devopedia. 2018. "RISC-V Instruction Sets." Version 3, August 26. Accessed 2024-06-25. https://devopedia.org/risc-v-instruction-sets
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Last updated on
2018-08-26 16:53:21
embedded design open source

See Also

  • RISC-V Architecture
  • ARM Architecture
  • Reduced Instruction Set Computer
  • Instruction Set Architecture
  • Chisel (Language)
  • OVPsim